The memory technology of this invention is a non-volatile memory technology, similar to that used in EEPROMs, such as flash memories, metal-oxide-nitride-oxide-silicon (MONOS), and silicon-oxide-nitride-oxide-silicon (SONOS). In addition, technologies known as atomic layer deposited (ALD) of high-k dielectrics, in this case, HfO2 film, and low temperature exposure to a plasma discharge, are used in the method of the invention.
Gate dielectrics may be formed in a number of ways. Two distinct methods that show much promise are 1) ALD of high-k films and 2) low temperature plasma oxidation. Each method has been shown to produce a high quality gate dielectric that can be used in conventional MOSFET fabrication flows, each technique having its own advantages.
An important characteristic of material to be used as a gate dielectric is that it does not trap large quantities of charge. Both of the aforementioned fabrication techniques have been demonstrated to produce gate dielectrics having this important characteristic. However, plasma oxidation of an ALD high-k film results in a film in which a large amount of charge may be retained. This is an advantage when used in a non-volatile memory device, in the same fashion as conventional EEPROM, MONOS, or SONOS devices. The amount of charge and the ease of programming and erasing may offer significant advantages over the mentioned memory technologies. FIG. 1 depicts a simplified structure of a prior art MONOS device (a) 10, having a gate stack 12, which includes a gate TiN layer 14 formed over an oxide/nitride/oxide stack 16, all of which is formed on a p-well substrate 18, compared to a device fabricated according to the method of the invention (b), 20, which has a gate stack 22, including a gate TiN layer 24 formed on a layer of HfO2 26, formed by plasma oxidation on a substrate p-well 28. The advantages of a device formed according to the method of the invention are described later herein.
Patent Publication WO2003003473 A1, of Yamada et al., published Jan. 9, 2003, describes a non-volatile semiconductor memory cell having a insulating film having charge-trapping properties.
Patent Publication WO0113378 A1, of Kawamura, published Feb. 22, 2001, describes a non-volatile memory having multi charge-trapping regions.
U.S. Pat. No. 6,528,845 B1, to Bude et al., granted Mar. 4, 2003, describes a non-volatile memory device having a charge trapping layer.
U.S. Pat. No. 6,008,091, to Gregor et al., granted Dec. 28, 1999, describes a floating gate MOS transistor with a charge-trapping layer having a relatively low charge trap density.
U.S. Patent Publication No. 2002/000592 A1 of Fujiware, published Jan. 3, 2002, describes a non-volatile memory device having a carrier trap charge storing mechanism.